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Freescale Semiconductor Advance Information
Document Number: 34844 Rev. 3.0, 11/2008
10 Channel LED Backlight Driver with Integrated Power Supply
The 34844 is a high efficiency, LED driver for use in backlighting LCD displays from 10" to 20"+. Operating from supplies of 7V to 28V, the 34844 is capable of driving up to 160 LEDs in 10 parallel strings. Current in the 10 strings is matched to within 2%, and can be programmed via the I2C/SM-Bus interface. The 34844 also includes a Pulse Width Monitor (PWM) generator for LED dimming. The LEDs can be dimmed to one of 256 levels, programmed through the I2C/SM-Bus interface. Up to 65,000:1 (256:1 PWM, 256:1 Current DAC) dimming ratio. The integrated boost converter generates the minimum output voltage required to keep all LEDs illuminated with the selected current, providing the highest efficiency possible. The integrated boost selfclocks at a default frequency of 600kHz, but may be programmed via I2C to 150/300/600/1200 kHz. The PWM frequency can be set from 100Hz to 25kHz, or can be synchronized to an external input. If not synchronized to another source, the internal PWM rate outputs on the CK pin. This enables multiple devices to be synchronized together. The 34844 also supports optical/temperature closed loop operation and also features LED over-temperature protection, LED short protection, and LED open circuit protection. The IC also includes overvoltage protection, over-current protection, and under-voltage lockout. Features * Input voltage of 7.0 to 28V * Boost output voltage up to 60V, with Dynamic Headroom Control (DHC) * 3.0A integrated boost FET * Up to 50mA LED current per channel * 90% efficiency (DC:DC) * 10-channel current mirror with 2% current matching * I2C/SM-Bus interface * PWM frequency programmable or synchronizable from 100Hz to 25,000Hz * 32-Ld 5x5x1.0mm TQFN Package * Pb-free packaging designated by suffix code EP
7.0 to 28V
34844
LED DRIVER
EP SUFFIX (PB-FREE) 98ASA10800D 32-PIN QFN-EP
ORDERING INFORMATION
Device MC34844EP/R2 Temperature Range (TA) -40C to 105C Package 32 QFN-EP
Applications * * * * Monitors - up to 27 inch Personal Computer Notebooks GPS Screens Small screen Televisions
34844
VIN VDC1 VDC2 VDC3 COMP SLOPE SCK SDA PWM A0/SEN CK M/~S EN VDC1 ISET PIN NIN GND VOUT PGNDA PGNDB FAIL I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 VCC SWA SWB
Control Unit
VDC1
~
~
~
~
~
~
~
~
~
~
VDC1
Figure 1. Simplified Application Diagram (SM-Bus Mode)
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIN VDC1 VDC2 VDC3 COMP SLOPE VOUT CK EN M/~S PWM PWM GENERATOR I0 I1 I2 SCK SDA 10 CHANNEL 50mA CURRENT MIRROR I3 I4 I5 I6 I7 I8 ISET CURRENT DAC I9 CLOCK/PLL V SENSE FAIL BOOST CONTROLLER LDO OVP PGNDA PGNDB SWA SWB A0/SEN
I2C INTERFACE
PIN NIN
TEMP/OPTO LOOP CONTROL
OCP/OTP/UVLO
GND
Figure 2. 34844 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
COMP VOUT VDC2 VDC1 PWM 25 24 CK 23 VDC3 TRANSPARENT TOP VIEW QFN - EP 5MM X 5MM 32 LEAD EP GND 22 SLOPE 21 NIN 20 PIN 19 ISET 18 FAIL 17 I9 9 I1 10 I2 11 I3 12 I4 13 I5 14 I6 15 I7 16 I8 M/~S SCK 27 SDA 26
32 VIN 1 PGNDB 2 SWB 3 SWA 4 PGNDA 5 A0/SEN 6 EN 7 IO 8
31
30
29
28
EP = Exposed Pad
Figure 3. 34844 Pin Connections Table 1. 34844 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.
Pin Number 1 2 3 4 5 6 7 8 - 17 18 Pin Name VIN PGNDB SWB SWA PGNDA A0/SEN EN I0-I9 FAIL Pin Function Power Power Input Input Power Input Input Input Open Drain Formal Name Input voltage Power Ground Switch node B Switch node A Power Ground Device Select Enable LED Channel Fault detection Input supply Power ground Boost switch connection B Boost switch connection A Power ground Address select, device select pin or OVP HW control Enable pin (active high, internal pull-up) LED string connections Fault detected pin (open drain): No Failure = Low impedance Failure = High Impedance LED current setting resistor Positive input analog current control Definition
19 20 21 22 23 24 25
ISET PIN NIN SLOPE VDC3 CK PWM
Passive Input Input Passive Output Input/Output Input
Current set Positive current scale
Negative current scale Negative input analog current control Boost Slope Internal Regulator 3 Clock signal External PWM Boost slope compensation Setting resistor Decoupling capacitor for internal phase locked loop power Clock synchronization pin (input for M/~S = low - internal pull-up, output for M/~S = high) External PWM input (internal pull-down)
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PIN CONNECTIONS
Table 1. 34844 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.
Pin Number 26 27 28 29 30 31 32 EP Pin Name SDA SCK VDC1 COMP M/~S VDC2 VOUT GND Pin Function Bidirectional Bidirectional Output Passive Input Output Input Formal Name I2C data I2C clock Internal Regulator 1 Compensation pin Master/Slave selector Internal Regulator 2 Voltage Output Ground I2C data Line I2C clock line Decoupling capacitor for internal logic rail Boost converter Type compensation pin Selects Master Mode (1) or Slave Mode (0) Decoupling capacitor for internal regulator Boost Output voltage sense pin Ground Reference for all internal circuits other than Boost FET Definition
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MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Maximum Pin Voltages A0/SEN I0, I1, I2, I3, I4, I5, I6, I7, I8, I9,EN(4) VIN SWA, SWB, VOUT FAIL, PIN, NIN, ISET, M/~S, CK Maximum LED Current ESD Voltage(1) IMAX VESD +2000 +200 VMAX 7.0 45 30 65 6.0 55 mA V V Symbol Value Unit
Human Body Model (HBM) Machine Model (MM) THERMAL RATINGS Ambient Temperature Range Junction to Ambient Junction to Case Temperature(2) TA TJA TJC TJ TSTO Reflow(3) TPPRT
-40 to 105 32 3.5 150 -40 to 150 260
C C/W C/W C C C W
Temperature(2)
Maximum junction temperature Storage temperature range Peak Package Reflow Temperature During Power Dissipation TA = 25C TA = 70C TA = 85C TA = 105C
3.9 2.5 2.0 1.4
Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-2), and the Machine Model (MM) (AEC-Q100003), RZAP = 0 2. 3. 4. Per JEDEC51 Standard for Multilayer PCB Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 45V is the Maximum allowable voltage on all LED channels in off-state.
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ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table 3. Electrical Characteristics Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40C TA 105C, PGND = 0V, unless otherwise noted.
Characteristic SUPPLY Supply Voltage Supply Current when Shutdown Mode Manual & SM-Bus: EN = Low, SCK & SDA=Low, PWM = Low I C: EN = Low, SETI C bit = 1, CLRI C bit = 0, PWM = Low Supply Current when Sleep Mode SM-Bus: EN = low, SCK & SDA= Active, SETI2C bit = 0, PWM=Low, EN bit = 0 I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 0, PWM=Low Supply Current when Operational Mode Boost=Pulse Skipping, Channels = 0% of Duty Cycle Manual: EN= High, SCK & SDA=Low, PWM=Low SM-Bus: EN= Low, SCK & SDA=Active, EN bit= 1, PWM=Low I2C: EN = High, SETI2C bit = 1, CLRI2C bit = 0, EN bit = 1, PWM=Low Under-voltage Lockout VIN Rising Under-voltage Hysteresis VIN Falling VDC1 Voltage(5) CVDC1 = 2.2F VDC2 Voltage(5) CVDC2 = 2.2F VDC3 Voltage(5) CVDC3 = 2.2F BOOST Output Voltage Range(6) VIN = 7.0V VIN = 28V Boost Switch Current Limit RDSON of Internal FET IDRAIN= 1.0A Boost Switch Off-state Leakage Current VSWA,SWB = 65V Peak Boost Efficiency(7) EFFBOOST 90 % IBOOST_LEAK 10 VOUT1 VOUT2 IFET RDSON 8.0 31 2.6 2.8 250 43 60 3.0 500 A m V VDC3 2.4 2.5 2.6 V VDC2 5.5 6.0 6.5 V VDC1 2.4 2.5 2.6 V UVLOHYST 150 200 250 mV UVLO 5.4 6.0 6.4 V IOPERATIONAL 10.0 mA ISLEEP
2 2 2
Symbol
Min
Typ
Max
Unit
VIN ISHUTDOWN
7.0
12
28
V
-
2.0 17 3.0
-
A
mA
A
Notes 5. This output is for internal use only and not to be used for other purposes 6. Minimum and Maximum output voltages are dependent on Min/Max duty cycle condition. 7. Guaranteed by design 34844
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ELECTRICAL CHARACTERISTICS
Table 3. Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40C TA 105C, PGND = 0V, unless otherwise noted.
Characteristic Line Regulation (8) VIN=7.0V to 28V Load Regulation (8) VLED = 8.0V to 65V (all Channels) Slope compensation voltage ramp RSLOPE = 68K Current Sense Amplifier Gain Current Sense Resistor OTA Transconductance Transconductance Sink and Source Current Capability Output Voltage Precharge FAIL PIN Off-state Leakage Current VFAIL = 5.5V On-state Voltage Drop ISINK = 4.0mA LED CHANNELS Sink Current ICHx Register = 255, RISET=5.1k 0.1%, PIN&NIN = Disabled, TA=25C Regulated minimum voltage across drivers Pulse Width > 4s Current Matching Accuracy ISET Pin Voltage RISET=5.1k 0.1% LED Current Amplitude Resolution 1.0mA < ILED < 50mA Off-state Leakage Current, All channels (VCH = 45V) PIN INPUT Voltage to Disable PIN mode PIN Bias Current PIN = VSET Analog Dimming Current ICHx Register = 255, RISET=5.1k 0.1% PIN = VSET/2 PIN = VSET Notes 8. Guaranteed by design 23.75 47.50 25 50 26.25 52.50 mA IDIM_PIN VPIN_DIS IPIN 2.2 -2.0 2.0 V A ICH_LEAK 10 A ILEDRES 1.5 % IMATCH VSET -2.0 2.017 2.048 2.0 2.079 % V VMIN 675 750 825 mV ISINK 49 50 51 mA VOL 0.4 V IFAIL_LEAK 5 A ACSA RSENSE GM ISS VHOLD 0.45 9.0 22 200 100 0.5 0.55 m S A V VSLOPE 0.49 V/s IOUT/VLED -0.2 0.2 %/V Symbol IOUT/VIN Min -0.2 Typ Max 0.2 Unit %/V
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ELECTRICAL CHARACTERISTICS
Table 3. Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40C TA 105C, PGND = 0V, unless otherwise noted.
Characteristic NIN INPUT Voltage to Disable NIN mode NIN Bias Current NIN = VSET Analog Dimming Current ICHx Register = 255, RISET=5.1k 0.1% NIN = VSET/2 NIN = 0V OVER-TEMPERATURE PROTECTION Over-temperature Threshold(9) Rising Hysteresis I2C/SM-BUS PHYSICAL LAYER [SCK, SDA] I2C Address SM-Bus Address Input Low Voltage Input High Voltage Input Hysteresis Output Low Voltage Sink Current < 4.0mA Input Current Input Capacitance(9) LOGIC INPUTS / OUTPUTS (CK, M/~S, PWM, A0/SEN) Input Low Voltage Input High Voltage Input Hysteresis Input Current Output Low Voltage (CK) ISINK < 2.0mA Output High Voltage (CK) ISOURCE < 2.0mA Input Capacitance(9) Notes 9. Guaranteed by design CINI 5.0 F VOHL 2.2 5.5 V VILL VIHL VHYSL IIIL VOLL -0.3 1.5 -5.0 0.1 0.5 5.5 5.0 0.2 V V V A V ADRI2C ADRSMB VILI VIHI VHYSI VOLI IINI CINI -0.3 2.1 0.3 -5.0 1110110 1110110 0.8 5.5 0.4 5.0 10 Binary Binary V V V V A F OTT 150 165 25 175 C 23.75 47.50 25 50 26.25 52.50 mA IDIM_NIN VNIN_DIS ININ 2.2 -2.0 2.0 V A Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS
Table 3. Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40C TA 105C, PGND = 0V, unless otherwise noted.
Characteristic OVER-VOLTAGE PROTECTION Over-voltage Clamp - OVP Register Table: OVP = Fh OVP = Eh OVP = Dh OVP = Ch OVP = Bh OVP = Ah OVP = 9h OVP = 8h OVP = 7h OVP = 6h OVP = 5h OVP = 4h OVP = 3h OVP = 2h Over-voltage threshold, Set by Hardware, Voltage at A0/SEN A0/SEN Sink Current BOOST Switching Frequency (BST [1:0]=0) Switching Frequency (BST [1:0]=1) Switching Frequency (BST [1:0]=2) Switching Frequency (BST [1:0]=3) Minimum Duty Cycle Maximum Duty Cycle Soft Start Period Boost Switch Rise Time(9) Boost Switch Fall Time(9) Notes 10. Guaranteed by design fSW0 fSW1 fSW2 fSW3 DMIN DMAX tSS tTR tF 0.14 0.27 0.54 1.08 80 0.15 0.30 0.60 1.2 10 85 6.5 15 25 0.17 0.33 0.66 1.32 15 MHz MHz MHz MHz % % ms ns ns ISINK_OVP 100 A OVPFH OVPEH OVPDH OVPCH OVPBH OVPAH OVP9H OVP8H OVP7H OVP6H OVP5H OVP4H OVP3H OVP2H OVPHW 60.5 56.5 53 49 45 41 38 34 30.5 26 23 19 15 11 6.15 62.5 58 54 51 47 43 39 36 32 28 24 20 16 12 6.5 64.5 60 56 52.5 48.5 44.5 40.5 37.5 33.5 30 25 21 17 13 6.85 V V V V V V V V V V V V V V V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS
Table 3. Electrical Characteristics (continued) Characteristics noted under conditions VIN = 12V, VOUT = 42V, ILED = 50mA, PWM = VDC1, M/~S = VDC1, PIN & NIN = VDC1, - 40C TA 105C, PGND = 0V, unless otherwise noted.
Characteristic PWM GENERATOR Input PWM Frequency Range (12) M/~S = Low (Slave Mode) PWM Frequency M/~S = High (Master Mode) FPWM Register = 768 FPWM Register = 192,000 PWM dimming resolution PWM PIN (DIRECT PWM CONTROL) Input PWM Pin Minimum Pulse(12) Input PWM Frequency Range PHASE LOCK LOOP CK Slave Mode Frequency Lock Range(11) M/~S = Low (Slave Mode) CK Slave Mode Input Jitter(12) M/~S = Low (Slave Mode) Slave Mode Acquisition Time M/~S = Low (Slave Mode) FPWMS=25KHz FPWMS=100Hz CK Frequency (Master Mode) FPWM Register = 768 FPWM Register = 192,000 I2C/SM-BUS PHYSICAL LAYER [SCK, SDA] Interface Frequency Range SM-Bus Power-on-Reset Time Output fall time 10F < CL < 400F Output rise time 10FNotes 11. Special considerations should be made for frequencies between 100Hz to 1KHz. Please refer to Functional Device Operation for further details. 12. Guaranteed by design
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
LED backlighting has become very popular for small and medium LCDs, due to some advantages over other backlighting schemes, such as the widely used cold cathode fluorescent lamp (CCFL). The advantages of LED backlighting are low cost, long life, immunity to vibration, low operational voltage, and precise control over its intensity. However, there is an important drawback of this method. It requires more power than most of the other methods, and this is a major problem if the LCD size is large enough. To address the power consumption problem, solid state optoelectronics technologies are evolving to create brighter LEDs with lower power consumption. These new technologies together with highly efficient power management LED drivers are turning LEDs, a more suitable solution for backlighting almost any size of LCD panel, with really conservative power consumption. One of the most common schemes for backlighting with LED is the one known as "Array backlighting". This creates a matrix of LEDs all over the LCD surface, using defraction and diffused layers to produce an homogenous and even light at the LCD surface. Each row or column is formed by a number of LEDs in series, forcing a single current to flow through all LEDs in each string. Using a current control driver, per row or column, helps the system to maintain a constant current flowing through each line, keeping a steady amount of light even with the presence of line or load variations. They can also be use as a light intensity control by increasing or decreasing the amount of current flowing through each LED string. To achieve enough voltage to drive a number of LEDs in series, a boost converter is implemented, to produce a higher voltage from a smaller one, which is typically used by the logical blocks to do their function. The 34844 implements a single channel boost converter together with 10 input channels, for driving up to 16 LEDs per string to create a matrix of more than 160 LEDs. Together with its 90% efficiency and I2C programmable or external current control, among other features, makes the 34844 a perfect solution for backlighting small and medium size LCD panels, on low power portable and high definition devices.
FUNCTIONAL PIN DESCRIPTION INPUT VOLTAGE SUPPLY (VIN)
IC Power input supply voltage, is used internally to produce internal voltage regulation (VDC1, VDC3) for logic functioning, and also as an input voltage for the boost regulator.
IC ENABLE (EN)
The active high enable terminal is internally pulled high through pull-up resistors. Applying 0V to this terminal would stop the IC from working.
INTERNAL VOLTAGE REGULATOR 1 (VDC1)
This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2F should be connected between this pin and ground for decoupling purposes.
INPUT/OUTPUT CLOCK SIGNAL (CK)
This terminal can be used as an output clock signal (master mode), or input clock signal (slave mode), to synchronize more than one device.
INTERNAL VOLTAGE REGULATOR 2 (VDC2)
This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2F should be connected between this pin and ground for decoupling purposes.
MASTER/SLAVE MODE SELECTION (M/~S)
Setting this pin High puts the device into Master mode, producing an output synchronization clock at the CK terminal. Setting this pin low, puts the device in Slave mode, using the CK pin as an input clock.
INTERNAL VOLTAGE REGULATOR 3 (VDC3)
This pin is for internal use only, and not to be used for other purposes. A capacitor of 2.2F should be connected between this pin and ground for decoupling purposes.
EXTERNAL PWM INPUT (PWM)
This terminal is internally pulled down. An external PWM signal can be applied to modulate the LED channel directly in absence of an I2C interface.
BOOST COMPENSATION PIN (COMP)
Passive terminal used to compensate the boost converter. Add a capacitor and a resistor in series to GND to stabilize the system.
CLOCK I2C SIGNAL (SCK)
Clock line for I2C communication.
ADDRESS I2C SIGNAL (SDA)
Address line for I2C communication.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
A0/SEN
Address select, device select pin, or Hardware Over voltage Protection (OVP) Control.
applying a voltage higher than 2.2V, the scaling factor is disabled and the internal pull-ups are activated in both pins.
GROUND (GND)
Ground Reference for all internal circuits other than the Boost FET. The Exposed Pad (EP) should be used for thermal heat dissipation.
CURRENT SET (ISET)
Each LED string can drive up to 50mA. The maximum current can be set by using a resistor from this pin to GND.
POSITIVE CURRENT SCALING (PIN)
Positive current scaling factor for the external analog current control. Applying 0V to this pin, scales the current to 0%, and in the same way, applying 2.048V(Vset), the scale factor is 100%. By applying a voltage higher than 2.2V, the scaling factor is disabled, and the internal pull-ups are activated. If PIN pin and NIN pin are used at the same time then by applying 0V to the PIN pin and 2.048V to NIN pin, scales the current to 0%, and in the same way, applying 2.048V to the PIN pin and 0V to NIN pin, scales the current to 100%. By applying a voltage higher than 2.2V, the scaling factor is disabled and the internal pull-ups are activated in both pins.
I0-I9
Current LED driver, each line has the capability of driving up to 50mA.
FAULT DETECTION PIN (FAIL)
When a fault situation is detected, this pin goes into high impedance.
BOOST SLOPE COMPENSATION SETTING RESISTOR (SLOPE)
Use an external resistor of about 68k to configure the Boost compensation slope.
NEGATIVE CURRENT SCALING (NIN)
Negative current scaling factor for the external analog current control. Setting 0V to this pin scales the current to 100%, in the same way, setting 2.048V (Vset) the scale factor is 0%. By applying a voltage higher than 2.2V, the scaling factor is disabled and the internal pull-ups are activated. If PIN pin and NIN pin are used at the same time then by applying 0V to the PIN pin and 2.048V to NIN pin, scales the current to 0%, and in the same way, applying 2.048V to the PIN pin and 0V to NIN pin, scales the current to 100%. By
POWER GROUND TERMINALS (PGNDA, PGNDB)
Ground terminal for the internal Boost FET.
OUTPUT VOLTAGE SENSE TERMINAL (VOUT)
Input terminal to monitor the output voltage. It also supplies the input voltage for the internal regulator 2 (VDC2).
SWITCHING NODE TERMINALS (SWA, SWB)
Switching node of boost converter.
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34844 - Functional Block Diagram Regulators / Power Down 3 Internal Regulators Protection / Failure Detection Over-temperature Protection Over-current Protection Under-voltage Protection Over-voltage Protection LED Open Protection Logic Control Optical and Temperature Control PWM Dimming Serial Interface Control
Regulator / Power down Protection / Failure Detection LED Channels Logic Control Boost
Boost
LED Channels
Figure 4. Functional Internal Block Diagram
REGULATORS/ POWER DOWN
The 34844 is designed to operate from input voltages in the 7.0 to 28V range. This is stepped down internally by LDOs to 2.5V (VDC1 and VDC3) and 6V (VDC3) for powering internal circuitry. If the input voltage falls below the UVLO threshold, the device automatically enters in power down mode. Operating Modes: The device can be operated by the EN pin and/or SDA/ SCK bus lines, resulting in three distinct operation modes: * Manual mode, there is no I2C capability, the bus line pins must be tied low, and the EN pin controls the ON/OFF operation.
* SM-Bus mode, EN pin must be tied low and the device is turned ON by any activity on the bus lines. The part shuts down if the bus lines are held low for more than 27ms, the 27ms watchdog timer can be disabled by I2C (setting SETI2C bit high) or tying the EN pin high. In Sleep mode (EN bit=1) the device reduces the power consumption by leaving "alive" only the blocks required for I2C communication. * I2C mode, has to be configured by I2C communication (SETI2C bit = 1) right after the IC is turned ON, it prevents the part from being turned ON/OFF by the bus. Sleep mode is also present and it is intended to save power, but still keep the IC prepared to communicate by I2C. Turning the EN pin OFF, the chip enters into a low power mode.
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MODE Manual
EN Pin Low High Low Low Low Low
SCK/SDA Pins Low Low Low (> 27ms) Active Active X
I2C Bit Command N/A N/A EN bit = X EN bit = 0 EN bit = 1 SETI2C bit = 1 CLRI2C bit = 0 EN bit = X SETI2C bit = 1
Current Consumption Mode Shutdown Operational Shutdown Sleep Operational I2C Low Power (Shutdown)
Comments
SM-Bus
Part Doesn't Wake-up
I2 C
High
X
CLRI2C bit = 0 EN bit = 0 SETI2C bit = 1
Sleep
High
X
CLRI2C bit = 0 EN bit = 1
Operational
Table 4. Operation Current Consumption Modes
BOOST
The integrated boost converter operates in nonsynchronous mode and integrates a 3A FET. An integrated sense circuit is used to sense the voltage at the LED current mirror inputs and automatically sets the boost output voltage (DHC) to the minimum voltage needed to keep all LEDs biased with the required current. The DHC is designed to operate under specific pulse width conditions in the LED drivers. It operates for pulse widths higher than 4s If the pulse widths are shorter than specified, the DHC circuit will not operate and the voltage across the LED drivers will increase to a value given by the OVP minus the total LED voltage in the LED string. Therefore it is imperative to select the proper OVP level to minimize power dissipation. The OVP can be set from 11 to 62V, ~4V spaced, using the I2C interface (OVP Register). If I2C capability is not present, the OVP can be controlled by a resistor divider connected from VOUT to GND with its mid point tied to A0/ SEN pin (threshold = 6.5V). During an OVP condition, the output voltage will go to the OVP level which is programmed via the I2C interface or settled by a resistor divider on A0/SEN pin, or by a zener diode. The formulas to calculate the hardware OVP using any of the two methods are as follows:
Method 1
VOUT
RUPPER A0/SEN RLOWER VZENER2 A0/SEN
OVP = VZENER2 + 6.5V
HARDWARE OVP: The OVP value should be set to greater than the maximum LED voltage over the whole temperature range. A good practice is to set it 5V or so above the max LED voltage. The boost converter also features internal Over-current Protection (OCP) and has a user programmable Overvoltage Protection (OVP). The OCP operates on a cycle by cycle basis. However, if the OCP condition remains for more than 10ms then the device turns off the LED Drivers, the Boost goes to Sleep Mode and the output FAULT pin goes into high impedance. The device can only be restarted by recycling the enable or creating a Power On Reset (POR). The user can program the boost frequency by I2C (BST[1:0]) only after the IC is powered up and before the boost circuit is turned ON for the first time (PWM pin low to high). This sequence avoids boost frequency to be changed inadvertently during operation. The first I2C command has to wait for 5.0ms after the part is turned ON, in order to allow sufficient time for the device power up sequence to be completed. The boost controller has an integral track and hold amplifier with indefinite hold time capability, to enable immediate LED on cycles after extended off times. During extended off times, the external LEDs cool down from their normal quiescent operating temperature and thereby experience a forward voltage change, typically an increase in the forward voltage. This change can be significant for applications with a large number of series LEDs in a string operating at high current. If the boost controller did not track this increased change, the potential on the LED drivers would saturate for a few cycles once the LED channels are reenabled.
Method 2
OVP = 6.5V [(RUPPER / RLOWER) + 1] + (100E-6 x RUPPER)
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Also the device has a precharge voltage that add 0.5 Volts to the Boost, cycle by cycle of the PWM. It helps the boost to respond faster every time the load turns back on again.
CURRENT MIRROR
The programmable current mirror matches the current in 10 LED strings to within 2%. The maximum current is set using a resistor to GND from the ISET pin. This can be scaled down using the I2C interface to 255 levels. Zero current is achieved by turning off the LED Driver by I2C (registers CHENx = 0h) for a Duty Cycle from 0% to 99% or by pulling PWM pin low regardless of the Duty Cycle. I2C capability allow the channels to be controlled individually or in parallel.
Current on LED Channel (PIN and NIN mode disabled) ICH [ RegisterValue ] Current [ A ] = ----------------------------------------------------------RSET [ ohms ] Eqn. 1
of the PWM duty cycle. This pin can also be used to modulate the LED at a lower frequency than the PWM dimming frequency (Minimum pulse width = 150ns). A pulsed mode can also be programmed using the I2C interface (STROBE bit = 1). In this mode, each rising edge of the PWM signal turns on the next channel, while turning off all other channels. The duration that the channel is illuminated is set by the duty cycle of the PWM input pin. This can be used to scan the output channels.
FAIL PIN
If an LED fails open, the voltage at the LED channel will be pulled to GND and the LED string open is detected. An error is registered for that channel, the fail output is set high, and that channel is turned off. The malfunction channel can be reenabled by I2C commands, first clearing the fail (CLRFAIL bit =1), removing the failure and then re-enabling the channel driver (Register CHEN). All fails are cleared when the device is powered up. If the fail pin cannot be cleared by software then it indicates that the failure is because of an over-current in the Boost. Since this is a critical failure the only way to clear it is by releasing the part from the over-current condition and then shutdown the part (refer to Table 4). If I2C communication is not present, FAIL condition should be reset by removing the failure and re-enabling the device through the EN pin.
In the off state, the LEDs current is set to 0 and the boost converter stops switching. This feature allows to drive more than 50mA of current by connecting the LED string to 2 or more LED channels in parallel. For example; if the application requires to drive 5 channels at 100mA, then the bottom of each LED string should be connected to two channels in order to duplicate the current capability (Example: CH0+CH1 = 100mA).
PWM GENERATOR
The PWM generator can operate in either master or slave modes, as set by the M/~S pin. In master mode, the internal PWM generator frequency is programmed through the I2C interface (registers FPWM). The default programmed value set the number of 25kHz clocks (40s) in one PWM cycle. The 18-bit resolution allows minimum PWM frequencies of 100Hz to be programmed. The resulting frequency is output on the CK pin.
PWM Frequency 19.2Mhz PWMFrequency [ Hz ] = ------------------------------------------------------------------FPWM [ RegisterValue ] Eqn. 2
OPTICAL AND TEMPERATURE CONTROL LOOP
The 34844 supports both optical and temperature loop control. For temperature loop control, the LED brightness can be adjusted depending on the temperature of the LEDs. For optical loop control, the 34844 supports both optical closed loop backlight control, where the brightness of the backlight is maintained at a required level by adjusting the light output, until the desired level is achieved, or with ambient light control, where the backlight brightness increases as ambient light increases. Both temperature and optical loops are supported through the PIN and NIN pins. Each pin supports a 0-2.048V input range which affects the current through the LEDs. The PIN pin increases current as the voltage rises from 0-2.048V. The NIN pin reduces current as the voltage rises from 0-2.048V. A 10.2k resistor or higher value must be used at the ISET pin if the part is configured to use PIN+NIN control loop functionality, the 50mA maximum current is achieved at the higher allowed level of PIN/NIN pins, ensuring the maximum current of the LED Drivers are not exceeded. The optical and temperature control loop can be disabled by I2C setting bits (PINEN & NINEN), or by tying PIN and NIN pins high (>2.2V) it is called Vset mode, and the LED Driver maximum current is set to 50mA by using a 5.1k resistor at the ISET pin.
In slave mode, the CK pin acts as an input. The internal digital PLL uses this frequency as the PWM frequency. By setting one device as master, and connecting the CK output to the input on a number of slave configured devices, all PWM frequencies are synchronized together. The duty cycle of the PWM waveform in both master and slave modes is set using a second register on the I2C interface (register DPWM), and can be controlled from 100% duty cycle to 1/256 Tpwm = 0.39%. Zero percent of duty cycle is achieved by turning LED Drivers off (register CHENx = 0h) or pulling PWM pin low. An external PWM can also be used. The PWM input is 'AND'ed with the internal signal. By setting the serial interface to 100% duty cycle (default), the external pin has full control
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Current on LED Channel (PIN mode) ( VPIN x ICH [ RegisterValue ] ) Current [ A ] = --------------------------------------------------------------------------------------RSET [ ohms ] Current on LED Channel (NIN mode) ( 2.048 - VNIN ) x ICH [ RegisterValue ] Current [ A ] = -----------------------------------------------------------------------------------------------------------RSET [ ohms ] Current on LED Channel (PIN+NIN mode)
Eqn. 3
Short LED Protection If an LED shorted in any of the LED strings, the device will continue to operate without interruption. However, if the shorted LED happens to be in the LED string with the highest forward voltage, the DHC circuit will automatically regulate the output voltage with respect to the new highest LED voltage. If more LEDs are shorted in the same LED string, it may cause excessive power dissipation in the channel which may cause the OTT circuit to trip which will completely shutdown the device.
Eqn. 4
Eqn. 5
( 2.048 - VNIN + VPIN ) x ICH [ RegisterValue ] Current [ A ] = ---------------------------------------------------------------------------------------------------------------------------------RSET [ ohms ]
OVER-TEMPERATURE PROTECTION
The 34844 has an on-chip temperature sensor that measures die temperature. If the IC temperature exceeds the OTT threshold, the IC will turn off all power sources inside the IC (LED drivers, boost and internal regulators) until the temperature falls below the falling OTT threshold. Once it comes back on, it will operate with the default configuration (please refer to Table 6).
LED FAILURE PROTECTION
Open LED Protection If LED fails open in any of the LED strings, the voltage in that channel will be pulled close to zero, which will cause the channel to be disabled. As a result, the boost output voltage will go to the OVP level and then come down to the regulation level to continue powering the rest of the LED strings.
SERIAL INTERFACE CONTROL
The 34844 uses an I2C interface capable of operating in standard (100kHz) or fast (400kHz) modes. The A0/SEN pin can be used an address select pin to allow more than 2 devices in the system. The A0/SEN pin should be held low on all chips expect the one to be addressed, where it is taken HIGH.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES NORMAL MODE
In normal operation the 34844 is programed via I2C to drive up to 50mA of current through each one of the LED channels. The 34844 can be configured in master or slave mode as set by the M/~S pin. In Master mode, the internal PWM generator frequency is programmed through the I2C interface. The programmed value sets the number of 25kHz clocks (40s) in one PWM cycle. The 18-bit resolution allows minimum PWM frequencies of 100Hz to be programmed. The resulting frequency is output on the CK pin. In slave mode, the CK pin acts as an input. The internal digital PLL uses this frequency as the PWM frequency. By setting one device as a master, and connecting the CK output to the input on a number of slave configured devices, all PWM frequencies are synchronized together. For this application A0/SEN pin indicates which device is enable for I2C control. In Slave mode, an internal phase lock loop will lock the internal PWM generator period to the period of the signal present at the CK pin. The PLL can lock to any frequency from 100Hz to 25KHz provided the jitter is below 1000ppm. At frequencies above 1KHz, the PLL will maintain lock regardless of the transient power conditions imposed by the user (i.e. going from 0% duty cycle to 100% at 20W LED display power). Below 1kHz, thermal time constants on the die are such that the PLL may momentarily lose lock if the die temperature changes substantially during a large load power step. As explained below, this anomaly can be avoided by controlling the rate of change in PWM duty cycle. To better understand this issue, consider that the on chip PLL uses a VCO that is subject to thermal drift on the order of 1000 ppm/C. Further consider that the thermal time constant of the chip is on the order of single digit milliseconds. Therefore, if a large power load step is imposed by the user (i.e. going from 0% duty cycle to 100% duty cycle with a load power of 20W), the die will experience a large temperature wave gradient that will propagate across the chip surface and thereby affect the instantaneous frequency of the VCO. As long as such changes are within the bandwidth of the PLL, the PLL will be able to track and maintain lock. Exceeding this rate of change may cause the PLL to lose lock and the backlight will momentarily be blanked until lock is reacquired. At 100Hz lock, the PLL has a bandwidth of approximately 10Hz. This means that temperature changes on the order of 100ms are tolerable without losing lock. But full load power changes on the order of 10ms (i.e. 100Hz PWM) are not tracked out and the PLL can momentarily lose lock. If this happens, as stated above, the LED drivers are momentarily disabled until lock is reacquired. This will be manifested as a perceivable short flash on the backlight immediately after the load change. To avoid this problem, one can simply limit large instantaneous changes in die temperature by invoking only small power steps when raising or lowering the display power at low PWM frequencies. For example, to maintain lock while transitioning from 0% to 100% duty cycle at 20W load power and a PWM frequency of 100Hz would entail stepping the power at a rate not to exceed 1% per 10ms. If a load of less than 20W is used, then the rate of rise can be increased. As the locked PWM frequency increases (i.e. use 600Hz instead of 100Hz), the step rate can be further increased to approximately 4% per 2ms. The exact step rate to avoid loss of PLL lock is a function of essentially three things: (a) the composite thermal resistance of the user's PCB assembly, (b) the load power, and (c) the PWM frequency. For all cases below 1KHz, simply using a rate of 1% duty cycle change per PWM period will be adequate. If this is too slow, the value can be optimized experimentally once the hardware design is complete. At PWM rates above 1KHz, it is not necessary to control the rate of change in PWM duty cycle. It is important to point out that when operating in the master mode, one does not need to concern themselves with loss of lock since the reference clock and the VCO clock are collocated on the die and therefore experience the same thermal shift. Hence, in master mode, once lock is initially acquired, it is not lost and no blanking of the display occurs. The duty cycle of the PWM in both master and slave mode is set using a second register on the I2C interface. An external PWM signal can also be applied in the PWM pin. This pin is AND'ed with the internal signal, giving the ability to control the duty cycle either via I2C or externally by setting any of the 2 signals to 100% duty cycle.
STROBE MODE
A strobe mode can be programmed via I2C. In this mode, each rising edge of the PWM signal turns on the next channel, while turning off all other channels. The duration that the channel is illuminated is set by the duty cycle of the PWM input pin. This mode can be also programmed by controlling the ON and OFF state of each LED channel via I2C.
MANUAL MODE
The 34844 can also be used in Manual mode without using the I2C interface. By setting the pin M/~S High, the LED dimming will be controlled by the external PWM signal. The over-voltage protection limit can be settled by a resistor divider on A0/SEN pin. During manual mode, all internal Registers are in Default Configuration, please refer Table 6, under this configuration
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
the PIN and NIN pins are enabled to scale the current capability per string and may be disable by setting 2.2V in the corresponding terminal. Also in this mode, the device can be enabled as follows: + EN pin + PWM signal (Two Signals): In this configuration the PWM signal applied to PWM pin will be in charge of controlling the LED dimming and a second signal will enable or disable the chip through the EN pin. Figure 17 + PWM Signal tied to SDA pin (Just ONE signal): In this configuration the PWM pin should be tied to SDA pin. The PWM signal applied to PWM pin will be in charge of
controlling LED dimming and enable the device every time the PWM is active. For this configuration EN pin should be LOW.
POWER DOWN MODE
If the input voltage falls below the UVLO threshold, the device enters automatically into power down mode. The device operates only when the EN pin is high, or the EN bit in Register 2 is set high. When in power down, the supply current is reduced below 2A when there is no I2C activity, and it rises up when I2C interface is enabled.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
Table 5. Write Registers
REG / DB D7
00 01 04 05 06 07 08 09 14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA ICH0_7 ICH1_7 ICH2_7 ICH3_7 ICH4_7 ICH5_7 ICH6_7 ICH7_7 ICH8_7 ICH9_7 ICHG_7 STRB DPWM7 OVP3
D6
OVP2
D5
OVP1
D4
OVP0
D3
D2
NINEN
D1
PINEN CLRI2C
D0
EN SETI2C FPWM0 FPWM6 FPWM12 DPWM0 CHEN0 CHEN5 BST0 ICH0_0 ICH1_0 ICH2_0 ICH3_0 ICH4_0 ICH5_0 ICH6_0 ICH7_0 ICH8_0 ICH9_0 ICHG_0
FPWM5 FPWM11 FPWM17 DPWM6 DPWM5
FPWM4 FPWM10 FPWM16 DPWM4 CHEN4
FPWM3 FPWM9 FPWM15 DPWM3 CHEN3 CHEN8
FPWM2 FPWM8 FPWM14 DPWM2 CHEN2 CHEN7
FPWM1 FPWM7 FPWM13 DPWM1 CHEN1 CHEN6 BST1
CLRFAIL
ALL_OFF
CHEN9
ICH0_6 ICH1_6 ICH2_6 ICH3_6 ICH4_6 ICH5_6 ICH6_6 ICH7_6 ICH8_6 ICH9_6 ICHG_6
ICH0_5 ICH1_5 ICH2_5 ICH3_5 ICH4_5 ICH5_5 ICH6_5 ICH7_5 ICH8_5 ICH9_5 ICHG_5
ICH0_4 ICH1_4 ICH2_4 ICH3_4 ICH4_4 ICH5_4 ICH6_4 ICH7_4 ICH8_4 ICH9_4 ICHG_4
ICH0_3 ICH1_3 ICH2_3 ICHG_3 ICH4_3 ICH5_3 ICH6_3 ICH7_3 ICH8_3 ICH9_3 ICHG_3
ICH0_2 ICH1_2 ICH2_2 ICH3_2 ICH4_2 ICH5_2 ICH6_2 ICH7_2 ICH8_2 ICH9_2 ICHG_2
ICH0_1 ICH1_1 ICH2_1 ICH3_1 ICH4_1 ICH5_1 ICH6_1 ICH7_1 ICH8_1 ICH9_1 ICHG_1
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 6. Register Description
DEFAULT VALUE DESCRIPTION (HEX) 1 1 1 F 0 0 300 FF 3FF 0 0 0 2 FF FF Chip Enable by software. This signal is `OR'ed with external EN (0=off, 1 =on) PIN pin enable (0=off, 1 =on) NIN pin enable (0=off, 1 =on) OVP voltage SET I2C communication (Disable SM-Bus Mode) Clear set I2C PWM Frequency PWM Duty Cycle (FFh =100%) Channel Enable (0=off, 1=on) All 10 channels OFF at the same. In order to reactivate channels this bit should be clear. Clear fail if channels are re-enable. Strobe MODE (0=Parallel, 1=Strobe) Boost Frequency (150,300,600,1200 kHz) [0h=150Hz] Channel Current Program (FFh = Maximum Current) Global Current Program
REGISTER NAME EN PINEN NINEN OVP[3:0] SETI2C CLRI2C FPWM[17:0] DPWM[7:0] CHEN[9:0] ALL_OFF CLRFAIL STRB BST[1:0] ICH#[7:0] ICHG[7:0]
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 7. Over Voltage Protection
REGISTER (HEX) 2 3 4 5 6 7 8 9 A B C D E F OVP VALUE (VOLTS) 11 15 19 23 27 31 35 39 43 47 51 55 59 62
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL PERFORMANCE CURVES (TA=25C) LOGIC COMMANDS AND REGISTERS
TYPICAL PERFORMANCE CURVES (TA=25C)
95% 94% 93% 92% Efficiency (%) 91% 90% 89% 88% 87% 86% 85% 10 12 14 16 18 20 Vin, volts 22 24 26 28 30 Fs = 600KHz L=22uH, DCR=52mO Schottky V12P10-E3/86A COUT = 2x4.7F, 2x2.2F/100V FPWM=600Hz, 100% duty Load = 16 LEDs, 50mA/channel VLED = 48V, 1V /channel
Figure 5. Boost efficiency vs Input Voltage
50.50 50.45 50.40 50.35 50.30 50.25 50.20 50.15 50.10 50.05 50.00 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vin, volts Fs = 600KHz L=22uH, DCR=52mO Schottky V12P10-E3/86A COUT = 2x4.7F, 2x2.2F/100V FPWM=600Hz, 100% duty Load = 16 LEDs, 50mA/channel V LED = 48V, 1V /channel
ILED (highest VLED channel), mA
Figure 6. Line Regulation, Vin Changing
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL PERFORMANCE CURVES (TA=25C) LOGIC COMMANDS AND REGISTERS
50.0 45.0 40.0 LED Current, mA 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.4% 0.14 mA 25.0% 50.0% PWM Duty Cycle (%) 75.0% 99.6% 12.46 mA
FPWM=25KHz
50.01 mA 37.59 mA
25.03 mA
Figure 7. PWM Dimming Linearity
10.10 10.08 10.06 10.04 Bias Current, mA 10.02 10.00 9.98 9.96 9.94 9.92 9.90 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vin, volts I2C Mode SM_Bus Mode Manual Mode
Figure 8. Bias Current vs Input Voltage (Operational Mode)
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Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL PERFORMANCE CURVES (TA=25C) LOGIC COMMANDS AND REGISTERS
3.12 3.10 3.08 Bias Current, mA 3.06 3.04 3.02 3.00 2.98 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vin, volts I2C Mode SM_Bus Mode
Figure 9. Bias Current vs Input Voltage (Sleep Mode)
COMP
Vin=24V Load=16 LEDs, 50mA/channel VLED = 47V, 1V VOUT
INDUCTOR CURRENT
Figure 10. Boost Soft Start
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL PERFORMANCE CURVES (TA=25C) LOGIC COMMANDS AND REGISTERS
ILED, CH1
ISET=40mA (all channels) FPWM=600Hz, 40% duty
VCH1
VOUT (ac coupled) Precharge
INDUCTOR CURRENT
Figure 11. Typical Operation Waveforms for FPWM=600Hz, 40% Duty
SWA SWB
INDUCTOR CURRENT VOUT (ac coupled)
ILED, CH1
ISET=50mA (all channels) FPWM=600Hz, 100% duty
Figure 12. Typical Operation Waveforms for FPWM=600Hz, 100% Duty
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TYPICAL PERFORMANCE CURVES (TA=25C) LOGIC COMMANDS AND REGISTERS
VCh1
ISET = 20mA, FPWM=20KHz, Duty=0.78% (2LSB)
ILED1
Figure 13. Low Duty Dimming Operation Waveforms (FPWM=20KHz, 2LSB)
VCh1
ISET = 20mA, FPWM=20KHz, Duty=0.39% (1LSB)
ILED1
Figure 14. Low Duty Dimming Operation Waveforms (FPWM=20KHz, 1LSB)
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS LOGIC COMMANDS AND REGISTERS
TYPICAL APPLICATIONS
MANUAL MODE (Single Wire Control)
VIN = 24V U1 1 47uF + 2.2uF 28 31 23 2.2uF 2.2uF 5.6K 1.8nF 309K 29 22 VIN VDC1 VDC2 VDC3 COMP SLOPE CK EN PWM SCK SDA A0/SEN M/~S ISET PIN NIN 34844 SWA SWB VOUT PGNDA PGNDB FAIL I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 GND 4 3 32 5 2 18 8 9 10 11 12 13 14 15 16 17 33 3.3K VCC 2 D1 1 22uH 1 2 VOUT
LED MATRIX (16S10P)
13.8uF +
0
56pF
0
0
Master CK Output 24 7 25
0
CLK
0
VOUT
150K OVP = 55V 20K 5.1K VDC1
0
VDC1
27 26 6 30 19 20 21
0
0
Figure 15. Manual Mode (Single Wire Control)
MANUAL MODE (Two Wire Control)
VIN = 24V U2 1 47uF + 2.2uF 28 31 23 2.2uF 2.2uF 5.6K 1.8nF 309K 29 22 VIN VDC1 VDC2 VDC3 COMP SLOPE CK EN PWM SCK SDA A0/SEN M/~S ISET PIN NIN 34844 SWA SWB VOUT PGNDA PGNDB FAIL I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 GND 4 3 32 5 2 18 8 9 10 11 12 13 14 15 16 17 33 3.3K VCC 2 D5 1 22uH 1 2 VOUT
LED MATRIX (16S10P)
13.8uF +
0
56pF
0
0
Master CK Output 24 7 25 27 26
Control Unit
EN PWM VOUT 150K
0
0
OVP = 55V 20K 5.1K VDC1
0
VDC1
6 30 19 20 21
0
0
Figure 16. Manual Mode (Two Wire Control)
VIN = 24V U3 1 47uF + 2.2uF 28 31 23 2.2uF 2.2uF 5.6K 1.8nF 309K 29 22 24 7 25 27 26 6 30 19 20 21 VIN VDC1 VDC2 VDC3 COMP SLOPE CK EN PWM SCK SDA A0/SEN M/~S ISET PIN NIN
22uH 1 2 VOUT 4 3 32 5 2 18 8 9 10 11 12 13 14 15 16 17 33 3.3K VCC 2 D8 1
LED MATRIX (16S10P)
SWA SWB VOUT PGNDA PGNDB FAIL I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 GND 34844
13.8uF +
0
56pF
0
0
Master CK
0
0
0
VDC1
Control Unit
SCK SDA VDC1 5.1K VDC1
0
0
Figure 17. SM-Bus Mode
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TYPICAL APPLICATIONS LOGIC COMMANDS AND REGISTERS
TYPICAL APPLICATIONS
MASTER - SLAVE Connection
VIN = 24V U4 1 47uF + 2.2uF 28 31 23 2.2uF 2.2uF 5.6K 1.8nF 309K 29 22 24 7 25 27 26 VDC1 5.1K VDC1 6 30 19 20 21 VIN VDC1 VDC2 VDC3 COMP SLOPE CK EN PWM SCK SDA A0/SEN M/~S ISET PIN NIN 34844 A0/SEN (Master) A0/SEN (Slave) SDA SCK SWA SWB VOUT PGNDA PGNDB FAIL I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 GND 4 3 32 5 2 18 8 9 10 11 12 13 14 15 16 17 33 3.3K VCC 2 D1 1 22uH 1 2 VOUT
LED MATRIX (16S10P)
13.8uF +
0
56pF
0
0
Master CK
0
0
VDC1
0
0
Control Unit
MASTER Device SLAVE Device
22uH
VIN = 24V U5 1 47uF + 2.2uF 28 31 23 2.2uF 2.2uF 5.6K 1.8nF 309K 29 22 24 7 25 27 26 6 30 5.1K VDC1 19 20 21 VIN VDC1 VDC2 VDC3 COMP SLOPE CK EN PWM SCK SDA A0/SEN M/~S ISET PIN NIN
1
2 VOUT 4 3 32 5 2 18 8 9 10 11 12 13 14 15 16 17 33 3.3K VCC 2 D2 1
LED MATRIX (16S10P)
SWA SWB VOUT PGNDA PGNDB FAIL I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 GND 34844
13.8uF +
0
56pF
0
0
Input Master CK VDC1
0
0
0
0
Figure 18. Master - Slave Connection
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS COMPONENTS CALCULATION
COMPONENTS CALCULATION
The following formulas are intended for the calculation of all external components related with the Boost converter and Network compensation. In order to calculate a Duty Cycle, the internal losses of the MOSFET and Diode should be taken into consideration. Vout + V D - Vin D = -------------------------------------------Vout + V D - V SW The average input current depends directly to the output current when the internal switch is off. R Comp x 5 x G M x Iout x L Cout = ------------------------------------------------------------------( 1 - D ) x Vout x CSG The output voltage ripple (Vout) depends on the ESR of the Output capacitor, for a low output voltage ripple it is recommended to use Ceramic capacitors that usually have very low ESR. Since ceramic capacitor are expensive, Electrolytic or Tantalum capacitors can be mixed with ceramic capacitors to have a cheaper solution. Vout x Vout x F SW x L ESR Cout = -------------------------------------------------------------Vout x ( 1 - D ) The output capacitor should handle at least the following RMS current.
IoutIin avg = -----------1-D
Inductor For calculating the Inductor we should consider the losses of the internal switch and winding resistance of the inductor. ( Vin - V SW - ( Iin avg x rw ) ) x D L = --------------------------------------------------------------------------------Iin avg x r x F SW It is important to look for an inductor rated at least for the maximum input current.
DIrms Cout = Iout x -----------1-D
Vin x ( Vout - Vin ) Iin max = Iin avg + -----------------------------------------------2 x L x F SW x Vout
Network Compensation Since this Boost converter is current controlled, Type II compensation is needed. I order to calculate the Network Compensation, first we need to calculate all Boost Converter components. For this type of compensations we need to push out the Right Half Plane Zero to higher frequencies where it can't affect the overall loop significantly. Vout x ( 1 - D ) f RHPZ = --------------------------------------Iout x 2 x x L
2
Input Capacitor The input capacitor should handle at least the following RMS current. Vin x ( Vout - Vin ) Irms Cin = ------------------------------------------------ x 0.3 2 x L x F SW x Vout Output Capacitor For the output capacitor selection the internal current sense gain (CSG) and the Transconductance should be taken in consideration. The CSG is the internal RSense times the current sense amplifier gain (ACSA). CSG = A CSA x R Sense
The Crossover frequency must be set much lower than the location of the Right half plane zero f RHPZ f Cross = -------------5 Since our system has a fixed Slope compensation set by RSLOPE, RComp should be fixed for all configurations. R Comp = 5.6Kohm CComp1 and CComp2 should be calculated as follows:
2 C Comp1 = ------------------------------------------------------f Cross x R Comp x x 2
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TYPICAL APPLICATIONS COMPONENTS CALCULATION
GM C Comp2 = -------------------------6.28 x F SW
Slope Compensation Slope Compensation can be expressed either in terms of Ampers/Second or as Volts/Second, through the use of the transfer resistance. The following formula express the Slope Compensation in terms of V/s: ( Vout - Vin ) x CSG V SLOPE = --------------------------------------------------Lx2 Where "L" is in H In order to have this slope compensation, the following resistor should be set. 33 x10 R SLOPE = ------------------V SLOPE
3
Variable Definition D= Boost Duty Cycle Vout= Output Voltage VD= Diode Forward Voltage Vin= Input Voltage VSW= VDROP of Internal Switch Vout= Output Voltage Ripple Ratio Iinavg= Average Input Current Iout= Output Current Iinmax= Maximum input current r = Output Current Ripple Ratio IrmsCin= RMS current for Input Capacitor IrmsCout= RMS current for Output Capacitor L= Inductor rw= Inductor winding DC Resistance FSW= Boost Switching Frequency CSG= Current Sense Gain = 0.2 V/A ACSA= Current Sense Amplifier Gain = 9 RSense= Current Sense Resistor = 22mohm Cout= Output Capacitor RComp= Compensation Resistor GM= OTA Transconductance ESRCout= ESR of Output Capacitor fRHPZ= Right Half Plane Zero Frequency fCross= Crossover Frequency CComp1= Compensation Capacitor CComp2= Shunt Compensation Capacitor VSLOPE= Slope Compensation (V/s) RSLOPE= External Resistor for Slope Compensation
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS LAYOUT GUIDELINES
LAYOUT GUIDELINES RECOMMENDED STACK-UP
The following table shows the recommended layer stackup for the signals to have good shielding and Thermal Dissipation. Table 8. Layer Stacking Recommendations
Stack-Up Layer 1 (Top) Layer 2 (Inner 1) Layer 3(Inner 2) Layer 4 (Bottom) Signal Ground Signal Ground
SWITCHING NODE (SWA & SWB)
The components associated to this node must be placed as close as possible to each other to keep the switching loop small enough so that it does not contaminate other signals. However, care must be taken to ensure the copper traces used to connect these components together on this node are capable to handle the necessary current and voltage. As a reference, a 10mils trace with a thickness of 1 oz of copper is capable of handling one ampere. Traces for connecting the inductor, input and output caps should be as wide and short as possible to avoid adding inductance or resistance to the loop. The placement of these components should be selected far away from sensitive signals like compensation, feedback and internal regulators to avoid power noise coupling.
DECOUPLING CAPS
It is recommended to place decoupling caps of 100pf at the beginning and at the end of any power signal traces to filter high frequency noise. Decoupling caps of 100pf should be also placed at the end of any long trace to cancel antenna effects on it. These caps should be located as closed as possible to the point to be decoupled and the connection to GND should be as short as possible.
COMPENSATION COMPONENTS
Components related with COMP pin need to be placed as close as possibThe trace of the feedback signal (VOUT) should be routed perpendicularly or at 45 on a different layer to avoid coupling noise, preferably between ground or power planes.
SM-BUS/I2C COMMUNICATION AND CLOCK SIGNALS (SDA, SCK AND CK)
To avoid contamination of these signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform through the whole signal trace length.
DO
FEEDBACK SIGNAL
The trace of the feedback signal (VOUT) should be routed perpendicularly or at 45 on a different layer to avoid coupling noise, preferably between ground or power planes.
IInput C ap nput Cap uC Swiitchiing Node S wit chin g Node d
On State
Signal
Signal
Feedback Feedback F da Signall Signa Sg Compensatiiion C ompensa on e sat Outtputt Cap O u pu Cap Off State
Ground Planes Ground Plane
Figure 19. Recommended shielding for critical signals. These signals shall not run parallel to power signals or other clock signals in the same routing layer. If they have to cross or to be routed close to a power signal, it is a good practice to trace them perpendicularly or at 45 on a different layer to avoid coupling noise.
Figure 20. Feedback Signal Tracing
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
EP SUFFIX 32-PIN 98ASA10800D REVISION O 34844
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
EP SUFFIX 32-PIN 98ASA10800D REVISION O
34844
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PACKAGING PACKAGE DIMENSIONS
EP SUFFIX 32-PIN 98ASA10800D REVISION O
34844
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 3.0
DATE 11/2008
DESCRIPTION OF CHANGES * Initial Release
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34844 Rev. 3.0 11/2008

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